1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuit fabrication, and more specifically to a computer implemented method and software for automating flip-chip bump layout in integrated circuit package design.
2. Description of the Related Art
Microelectronic integrated circuits are packaged in a number of configurations. A type of integrated circuit 10 which is currently in widespread use is known as a xe2x80x9cflip-chipxe2x80x9d and is illustrated in FIGS. 1 to 3. The integrated circuit 10 includes a package 12 which includes a body 14, a plurality of pins 16 for connecting the circuit 10 to a socket of an electronic device such as a computer (not shown), and a plurality of bumps 18 on a surface of the package 12 opposite a surface from which the pins 16 extend. Although not visible in the drawing, the bumps 18 are connected to the pins 16 through interconnects inside the body 14 of the package 12. The interconnects can be formed in a number of layers that are separated by insulating layers and interconnected by vertical interconnects (vias).
The integrated circuit 10 further includes a microelectronic circuit die 20 which comprises a semiconductor substrate (silicon, gallium arsenide, etc.) that is processed to include a large number of microelectronic circuit devices. The die 20 can include devices which are interconnected to perform the functionality of a microprocessor, memory, input-output device, etc. A plurality of bumps 22 are formed on a surface of the die 20 and are electronically connected to the microelectronic devices through internal interconnect layers and vias (not shown). The bumps 22 on the die 20 are conjugate to the bumps 18 on the package 12.
The package 12 and the die 20 are fabricated separately and then assembled together such that the bumps 18 and 22 electrically contact each other and thereby interconnect the devices of the die 20 with the pins 16 of the package 12. This is typically accomplished by applying solder to either or both of the bumps 18 and 22, mating the die 20 and package 12 such that the bumps 18 and 22 contact each other, and applying heat to reflow the solder.
The configuration is called a xe2x80x9cflip-chipxe2x80x9d because the die 20 is flipped upside down for assembly to the package 12 such that the bumps 22 face downwardly (toward the package 12). When the die 20 is oriented with the bumps 22 facing up (the same as the bumps 18 of the package 12), the bumps 22 have a mirror image relationship relative to the bumps 18. For example, bumps 18a and 18b of the package 12 are conjugate to bumps 22a and 22b of the die 20 as viewed in FIG. 3.
It is typical for an integrated circuit manufacturer to fabricate dies, obtain packages from an independent supplier, and assemble the dies to the packages to provide complete integrated circuits for sale. Once an integrated circuit die is designed and the pattern of the bumps determined, the manufacturer provides the package supplier with the design so that a suitable package can be designed and manufactured.
Integrated circuit dies are typically designed using computer software which uses a format which is suitable for electronic circuit design. A number of commercial and proprietary circuit design software programs are in current use that produce data files in a format known as Calma GDSII, which is now an industry standard. However, integrated circuit packages are designed using different software programs which produce data files in a format which is incompatible with GDSII.
Current flip-chip integrated circuits have a large number, typically over 1,000, bumps such as illustrated at 22 in the drawings. The pattern of these bumps is known as a Control Collapse Chip Connection (C4) cage. The bumps are laid out in a generally orthogonal pattern including a certain maximum number of possible bump positions, but not all bump positions are used. When a package for a new die is to be designed, the package supplier is provided with the C4 cage and a netlist which indicates which bumps are to be connected to which pins in the package. The internal interconnections in the body 14 of the package 12 are designed in accordance with this data.
The C4 cage is generated by the circuit designer in GDSII format which is not usable by the package designer""s software. Conventionally, C4 cage data conversion has been performed manually by printing out the C4 cage pattern, visually examining the individual bumps, and manually entering representative data into the package design software program. This procedure is slow, tedious and highly prone to human error. Any kind of error in an integrated circuit design process is highly undesirable in that it necessitates time consuming and expensive changes in a number of fabrication areas.
In addition, the C4 cage pattern is often changed during the development of the die, and it is difficult to identify individual changes and appropriately modify the data for the package design program. Adapting for changes is especially prone to error since changes can be easily overlooked due to the large number of bumps.
The present invention overcomes the deficiencies of the prior art by providing a computer implemented method and program for automatically converting interconnect bump pattern data for a flip-chip integrated circuit which is produced by circuit design software in GDSII format to data which can be automatically input into package design software. The present method also enables changes in the bump pattern to be automatically identified.
In accordance with the present invention, a digital computer automatically converts an input representation of a pattern of flip-chip integrated circuit interconnect bumps in a format suitable for a circuit design program into an output representation in a format suitable for a package design program. A converter program is adapted by script files to convert the input representation into an intermediate representation in a format suitable for a mechanical design program in which only a layer which includes the bumps is extracted from the input representation which can include a substantial number of layers.
A mechanical design program is adapted by scripts to automatically input the intermediate representation, identify and label the interconnects, and create the output representation in which the interconnects are labeled. The mechanical design program can be further adapted by scripts to rotate, mirror and/or shrink the pattern. A package design program inputs the output representation and draws the labeled interconnects. A comparator program compares the output representation with a previously created output representation to identify differences therebetween.
The present invention greatly reduces the time required for creating data which is to be provided to an integrated circuit package supplier for designing or changing a package for a particular flip-chip integrated circuit die. The invention also eliminates human error from the procedure, thereby greatly improving the reliability of the design process.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.